40G PCB Design and Routing Guide

1. Characteristic Impedance

Printed microstrip line (surface layer): Z = 65Ω ± 10%;

Printed stripline (inner layer): Z = 50Ω ± 10%; differential clock single-ended impedance to ground: 50Ω, differential impedance: 100Ω.

2. Trace Width Recommendations: Signal trace width = 6 mils, trace width = 4.5 mils for difficult-to-route traces, power/ground trace width = 15 mils or 30 mils depending on the situation.

3. Stackup Recommendations: Refer to the stackup of the CS1999 reference design. Board thickness: 2.4 ± 0.2mm. The recommended number of layers should not exceed 16-18.

4. BGA chip pin vias: For unused pins, retain the lead-out vias as much as possible, except for those that affect routing.

1. Power supply types mainly include the following:

• P48V/N48V, 5V (40A), 2V5 (22A), 1V2 (60A), 1V8 (10A), 3V3

(10A), and 5V2N (3A), VDDQ, VTT, and VREF; these are digital power supplies.

• 3V3A, VCCTX_1/2, 1V2A_1/2: These are analog power supplies output by linear power modules.

2. For 5V (40A), 2V5 (22A), 1V2 (60A), 1V8 (10A), and 3V3 (10A), consider the current capability of the vias when connecting the power module output pins to the power splitter layer based on the current level.

It is recommended to add corresponding fill planes on multiple signal layers around the corresponding pins, and then use multiple vias to connect the layers to direct the current to the corresponding power layer.

3. The CS1999, FPGA, and optical modules have multiple analog power supplies. These are generally provided using linear power supplies or through LC filtering. All analog power supplies require power splitting. Analog power splitting is recommended: split on the signal layer, with the upper and lower adjacent layers required to be signal ground.

The following power supplies require splitting:

1) CS1999 analog power supplies:

STX0_VDD, STX1_VDD, SRX0_VDD, SRX1_VDD, HTX0_VDD, HTX1_VDD, HRX0_VDD,

HRX1_VDD, SFI5_VDD_DVR, HTX_VDD_DVR.

2) FPGA:

VCC_PLL_OUT1/2/3, VCCA_3V3_1, 2, VCCTX_1/2, 1V2A_1/2, VCCP_1/2.

3) Optical modules: 5V, 3V3, 1V8, 5V2N, and other analog power supplies are provided through LC filtering. 4) Other: All power supplies after inductor L.

4. All current vias for the 1008PS inductor should comply with the 3A requirement, and all others with 1A.

5. Ground Planes

This includes signal ground and chassis ground.

A chassis ground plane should be laid around each signal layer and connected to the corresponding socket.

6. During routing, the TAB planes for all LDO power conversion chips (LT1963AEQ, LT1764EQ, LP3883ES) must be defined and connected to the corresponding planes. The heat dissipation copper area should be appropriately increased, and a symmetrical copper plane should also be added on the back side (the area can be as large as possible if the layout allows). Connect these planes to the corresponding power or ground planes through multiple vias to facilitate heat dissipation. The TAB plane definitions for each chip are as follows:

LT1963A/LT1764/LP3883: TAB = GND (ground).

7. For the CS1999 power and ground separation, please refer to the actual layout files for the evaluation board.

1. Design and implement according to the logic diagram. Decoupling capacitors should be evenly spaced for each device. Small-value capacitors should be placed as close to the power pins as possible, and large-polarity capacitors should be placed around the chip.

2. Each of the two FPGAs has five pins, K7/T7/Y4/AD7/AK7. Connect an external 2.00kΩ resistor to ground. Keep these traces away from other interference sources. Use a ground ring to isolate these traces from other lines.

3. General decoupling capacitor connection requirements: The capacitor pad routing is as shown below:

1. General Requirements for Differential Signals:

• The lengths of differential pairs must be strictly matched, with a maximum error of <10 mil. All signal lines, except those with length requirements, should be as short as possible.
• Differential pairs should be kept as close together as possible (but to ensure impedance, a 6 mil line width and 6/9 mil spacing is recommended). Spacing between them should be >15 mil, and spacing between them should be >30 mil.
• Differential pairs should be routed on the same layer to minimize vias and layer changes (except where matching resistors are connected, only the source and destination terminals can change layers via vias).
• When power planes are split, adjacent differential signals on the same power plane cannot cross partitions.
• For terminations with matching resistors, the matching resistor connection methods are shown in the figure below. Select one of the following methods for connection.

The trace lengths should also follow the diagram.

For differential lines with series capacitors, the capacitors of the differential pair must be placed on the same side (generally close to the terminals) and have matching trace lengths. When using AC coupling for PECL clocks, the external resistor at the source is connected as shown in the figure below.

2. Clock Signals

• Differential Clocks

Includes the following signals:

The 622M clock has three pairs: MSA_RXREFCLK_P/N, MSA_TXREFCLK_P/N, and CS1999_REFCLK_P/N.

The 156M clock has eight pairs: IF_REFCLK1/2_P/N, XAUI_REFCLK1/2_P/N,

FPGA1/2_CORECLK_P/N, and CS1999_IL_REFCLK1/2_P/N.

For the routing and matching requirements for these signals, see above. Keep differential clock traces as far away from other signal lines as possible, especially parallel traces. Each differential pair does not need to be the same length as other differential pairs, but the maximum length should not exceed 15cm. Single-ended LVTTL clock signals

Includes the following signals: SRAM_CLK, TCAM_CLK

These signals should be routed as short as possible, typically less than 3cm and no longer than 5cm. The series 25 ohm resistor should be as close as possible to the source chip (FPGA) pin.

3. SFI5 Interface Signals

This signal is used for high-speed data (3.125G) transmission between the optical module and the CS1999, including both receive and transmit signals.

The signals are shown in the table below.

1) Use the appropriate bottom signal layer to minimize stub trace lengths; use arcs or 45° bends when routing.

2) Via Rules: Remove all pads on internal layers from all vias (retain only pads on the connection layer).

3) Refer to the CS1999 reference design layout files for detailed routing and via parameter recommendations.

4) Avoid routing receive and transmit differential pairs on the same layer.

4. Interlaken Interface Signals: These signals are used for high-speed data (3.125G) transmission between the CS1999 and the FPGA. Like SFI5, they include two groups: receive and transmit. The signals are shown in the table below.

For routing information, refer to the SFI5 signal routing requirements.

5. XAUI Signals

Used for high-speed signal transmission between the FPGA and the backplane ZD socket.

1) The length of the trace connected to the ZD socket should be <5" (including the total length of the traces at both ends of the series capacitor). The actual trace length should be as short as possible to minimize backplane trace length control. There are eight groups of signals:

LINE0_XAUI_RXDAT_P/N_<3.0> is a 4-pair 3.125G differential signal;

LINE1_XAUI_RXDAT_P/N_<3.0> is a 4-pair 3.125G differential signal;

LINE0_XAUI_TXDAT_P/N_<3.0> is a 4-pair 3.125G differential signal;

LINE1_XAUI_TXDAT_P/N_<3.0> is a 4-pair 3.125G differential signal;

LI NE2_XAUI_RXDAT_P/N_<3..0> is a 4-pair 3.125G differential signal.

LINE3_XAUI_RXDAT_P/N_<3..0> is a 4-pair 3.125G differential signal.

LINE2_XAUI_TXDAT_P/N_<3..0> is a 4-pair 3.125G differential signal.

LINE3_XAUI_TXDAT_P/N_<3..0> is a 4-pair 3.125G differential signal.

2) Each pair of differential lines should have a length tolerance of less than 10 mil. Each pair of four is not strictly required to be of equal length, but the tolerance should be minimized and the length kept as short as possible.

3) For routing, refer to SFI5 signal routing requirements.

6. 700M LVDS signals

Used for high-speed signal transmission between two FPGAs. Includes the following four groups:

The receive and transmit differential pairs should not be routed on the same layer. Other differential lines should follow general requirements.

7. HSTL Signals

The signals connecting U1 (NL3300) and IC2 are HSTL-1 signals operating at approximately 200MHz. Please route them according to general HSTL routing requirements.

1) The 50 Ω termination resistors for the bidirectional signals TCAM_DBUS[0:71] and the unidirectional signals CAM_CLK and TCAM_IBUS should be placed as close to U1 as possible, and their stub lines should be as short as possible. As shown in the figure below, it is recommended to follow routing (a). If routing is difficult, follow routing (b), keeping the termination resistor branch length and the distance between the replication point and the U1 pin as short as possible.

2) The following signal groups must be of equal length, with an error of <100 mil:

TCAM_CLK, TCAM_CLKO, TCAM_IBUS[7:0], TCAM_DBUS[71:0], TCAM_HITACK,

TCAM_VALID, TCAM_RDACK

3) VTT filter capacitors CP1 through CP10 should be evenly distributed around the termination resistors.

8. 100M Ethernet Signals

1) The following are differential signal pairs, with the same routing requirements as general differential signals.

100M_RD+/-, 100M_TD+/-, BACK_100M_TD+/-, BACK_100M_RD+/-, 100M_TX+/-,

100M_RX+/-, RJ_100M_TD+/-, RJ_100M_RD+/-.

2) The following signals are not differential signals, but each group must be of equal length:

MII_TX_CLK, MII_TXD<3.0>, and MII_TXEN are grouped together, with an error of <1cm.

MII_RX_CLK, MII_RXD<3.0>, MII_RXEN, MII_RXER, MII_RX_CRS, and MII_RX_COL are grouped together, with an error of <1cm.

9. Side Scan Signal Routing

a) TMS signal routing direction: Side Scan 2x5 socket -> FPGA1 (IC3) -> FPGA2 (IC4)

b) TCK signal routing direction is the same as TMS.

10. Control bus signals:

Includes LOCAL_AD[31:0], LOCAL_ACK, LOCAL_RW, LOCAL_RDY, LOCAL_STB, and LOCAL_ALE.

Connect each bus group in a daisy-chain fashion.

11. Other Data Bus Signals:

For all other grouped bus signals not mentioned above, ensure that each bus group does not differ significantly (maintain the same order of magnitude) and has the shortest possible length.

The indicators required to be displayed on the panel include three power and system status indicators and three 40G interface status indicators.

The relative positions of the indicators on the panel are shown in the figure below.

The corresponding relationship between the panel indicator lights and the LEDs on the logic diagram is as follows:

Please place the indicator lights according to the above relative positions and corresponding relationships.