Note: DDR signal topologies often encounter one-to-many signaling scenarios. This article uses DDR3 address lines as an example, comparing simulations of branches of different lengths to understand the impact of branch length on waveforms, thereby further addressing this issue in design.
Daisy-chain topology of 8 DDR3 address lines
Due to the daisy-chain principle, the DDR3-8 closest to the FPGA in the figure above reflects the reflections of the seven subsequent DDR3-8s, resulting in a relatively poor waveform. The following DDR3-8s, however, perform relatively well. Therefore, we will only examine the DDR3-8 waveform here to simplify the analysis.
Waveforms for branch lengths of 30 mils (red), 100 mils (blue), and 200 mils (green):
Waveforms when branch lengths are 200mil (red), 300mil (blue), and 500mil (green):
Waveforms when the branch length is 500mil (blue) and 1000mil (green):
As can be seen from the three figures above, shorter branch lengths result in better waveforms, while longer branch lengths result in worse waveforms. Taking all factors into consideration, for a daisy-chain topology with eight DDR3 address lines, it is recommended that the branch length be kept within 200 mils.
8 DDR3 address lines daisy-chain + T topology
Due to the daisy-chain principle, the DDR3-4/DDR3-8 closer to the FPGA in the figure above reflects the reflections of the six subsequent DDR3-4/DDR3-8 devices, resulting in a relatively poor waveform. The following devices, however, perform relatively well. Therefore, we only examine the DDR3-4/DDR3-8 waveforms here to simplify the analysis.
Waveforms for branch lengths of 30 mils (red), 100 mils (blue), and 200 mils (green):
Waveforms when branch lengths are 200mil (red), 300mil (blue), and 500mil (green):
Waveforms when the branch length is 500mil (blue) and 1000mil (green):
The three figures above show that shorter branch lengths produce better waveforms, while longer branch lengths deteriorate. The waveform deteriorates significantly at 300-mil branches and completely fails at 500-mil branches. Taking all factors into consideration, in a daisy-chain + T-type topology with eight DDR3 address lines, the T-type branches should be as short as possible, ideally using a reverse-mount pin swap method. The recommended branch length is around 100 mil, not too long.
Simulations comparing the two topologies show that the daisy-chain topology significantly improves signal quality when the branches are longer, and the daisy-chain topology is easier to control branch length. The daisy-chain + T-type topology, however, has relatively long branches and is difficult to shorten. Therefore, the daisy-chain topology is preferred in practical designs (the daisy-chain topology requires the controller chip to support Write Leveling).