Once the substrate material is selected, the stack-up structure becomes the second most critical aspect of high-frequency, high-speed PCB design. Standard PCB stacking strategies cannot simply be applied to high-frequency, high-speed products. The stack-up determines impedance control, signal return paths, crosstalk levels, and power integrity. Many projects show ideal simulation results, yet the signal eye diagrams deteriorate upon receiving the physical prototypes; often, the root cause lies in poor stack-up planning.
Core Design Principles for High-Frequency, High-Speed Stack-ups
First, prioritize placing signal layers immediately adjacent to a solid reference ground plane. High-speed differential traces and RF microstrip or stripline traces must have a continuous, uninterrupted reference plane. Discontinuities in the return path lead to significant signal loss, reflections, and EMI radiation-making them the primary "killer" of high-frequency, high-speed designs.
Second, maintain symmetry in the stack-up structure whenever possible. Asymmetry in dielectric materials or copper thicknesses between the top and bottom halves of the board can lead to severe warping after lamination. For high-layer-count, high-frequency, high-speed boards, warping causes SMT assembly defects and BGA solder joint failures.
Third, distinguish between the application scenarios for microstrip lines and striplines. Microstrip lines reside on the outer layer, exposed to air on one side and dielectric on the other, making them suitable for RF applications; however, surface signals are susceptible to external interference and generate significant radiation. Striplines are embedded between two ground planes, offering excellent shielding and stable loss characteristics; they are ideal for high-speed differential signals, though they require more board layers.
Fourth, impedance calculations must utilize broadband Dielectric Constant (Dk) parameters measured by the material manufacturer; default FR-4 parameters are insufficient. Even with identical trace widths, different materials have varying Dk values, and impedance deviations can directly cause signal reflections to exceed acceptable limits.
Analysis of Typical Stack-up Schemes
Recommended structure for an 8-layer high-speed digital board (e.g., AI acceleration cards, network switches): Signal – GND – Signal – PWR – GND – Signal – GND – Signal. High-speed signals are preferentially routed as striplines, flanked by solid ground planes above and below. The power plane is placed close to a corresponding ground plane to enhance power-to-ground plane coupling and improve PDN (Power Delivery Network) impedance. 4-layer high-frequency mixed-material board (optical module): Top layer for RF microstrip lines; second layer as a solid ground plane; third layer for power; bottom layer for standard digital signals. All RF traces are placed on the top layer, referencing the solid ground plane on the second layer; traces must not cross splits in the power plane.
For mixed-signal boards containing both RF and ultra-high-speed digital signals, assign RF and high-speed digital signals to different layers whenever possible. Avoid significant vertical overlap between them to minimize interlayer coupling and crosstalk.
Note: Do not use a split power plane as a reference directly beneath high-speed signal layers. If a trace crosses a split gap, the return current is forced to take a detour, causing impedance discontinuity and severely degrading signal integrity.
Via Management: Critical Impedance Discontinuity Points in High-Frequency/High-Speed Links
Vias are major sources of impedance discontinuity in high-frequency and high-speed links. Via stubs, parasitic capacitance, and inductance increase return loss-an effect particularly pronounced at high frequencies.
For data rates exceeding 25 Gbps, prioritize back-drilling to remove excess via stubs; for HDI products, prioritize blind and buried vias to eliminate stubs entirely. Use resin-filled "via-in-pad" structures for high-density BGA fan-outs to reduce signal loss caused by vias.
Carefully calculate via anti-pad dimensions. An anti-pad that is too small increases parasitic capacitance, while one that is too large compromises the integrity of the reference ground plane. When high-speed signals change layers, place adjacent stitching ground vias to provide a nearby return path, thereby minimizing signal degradation caused by the layer transition.
Asymmetry between the two vias of a high-speed differential pair is strictly prohibited; via pad and anti-pad dimensions must be identical. Otherwise, intra-pair skew increases, and common-mode noise rises.
Practical Guidelines for Routing and Impedance Control
Common impedance targets are 100Ω for differential pairs and 50Ω for RF single-ended lines. Impedance tolerances for high-frequency/high-speed boards typically require ±5%; millimeter-wave RF applications may require ±3%-far stricter than the standard ±10% for conventional PCBs. Intra-pair length mismatch for differential pairs is strictly controlled, with tolerances varying by data rate; for instance, PCIe 5.0 requires control within ±5 mils-the higher the speed, the stricter the length-matching constraint. Sufficient spacing is maintained between differential pairs, adhering to the "3W rule" to minimize crosstalk and avoid long-range parallel coupling.
For RF traces, via usage is minimized; microstrip RF signals are prioritized over inner-layer striplines, as layer transitions introduce impedance discontinuities. RF trace corners utilize arcs rather than 90-degree angles to reduce signal reflection.
Regarding power delivery, the design of the Power Delivery Network (PDN) for high-frequency, high-speed boards is critical. Power and ground planes are tightly coupled, with numerous decoupling capacitors placed in close proximity. Reference ground planes for high-speed signals must not be split; digital-analog partitioning should be achieved through component placement rather than arbitrary ground plane segmentation.
Common Pitfalls in High-Frequency, High-Speed Design
Failing to have the stack-up design verified by the manufacturer immediately after completion. Manufacturers may lack the specific prepreg (PP) sheets required for certain dielectric thickness combinations, making the target impedance unachievable and necessitating a design revision.
Overlooking the "Glass Weave Effect." In ultra-high-speed links, aligning traces with the glass fiber weave pattern can cause impedance fluctuations along the trace. Whenever possible, account for the impact of the glass weave effect during simulation and design.
Lack of control over solder mask thickness for surface-layer RF traces. Solder mask covering RF microstrip traces alters the effective dielectric constant, leading to impedance shifts; consider using solder mask openings (windows) in high-frequency RF microstrip areas.
Relying solely on schematic-level simulation without incorporating PCB stack-up, via, and material parameters into channel simulation. Idealized simulation models often diverge significantly from the actual physical hardware.
The stack-up design determines the board's performance ceiling. Even with perfect routing, flaws in the stack-up are difficult to rectify during the debugging phase. We also provide prototyping and mass production services for high-frequency, high-speed PCBs.